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DATA SHEET
O K I A S I C P R O D U C T S
MSM30R/32R/92R 0.5m Sea Of Gates and Customer Structured Arrays
August 2002
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CONTENTS Description ................................................................................................................................................................1 Features ....................................................................................................................................................................1 MSM30R/32R/92R Family Listing .......................................................................................................................2 Array Architecture ...................................................................................................................................................3 MSM92R000 CSA Layout Methodology ........................................................................................................3 Electrical Characteristics .........................................................................................................................................5 Macro Library .........................................................................................................................................................10 Macrocells for Driving Clock Trees ..............................................................................................................11 Oki Advanced Design Center Cad Tools ..........................................................................................................1 2 Design Process .................................................................................................................................................13 Automatic Test Pattern Generation ..............................................................................................................14 Floorplanning Design Flow ...........................................................................................................................14 IEEE JTAG Boundary Scan Support .............................................................................................................15 Package Options .....................................................................................................................................................16
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MSM30R/32R/92R
Second-Generation 0.5m Sea of Gates and Customer Structured Arrays DESCRIPTION
Oki's second-generation 0.5m ASIC products are available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. The MSM30R Series, MSM32R Series, and MSM92R Series all offer increased density over their first-generation counterparts, as well as 3-V I/O buffers that are 5-V tolerant. Both the SOG-based MSM30R Series and the CSA-based MSM92R Series use a three-layer metal process on 0.5m drawn (0.4m L-effective) CMOS technology. The SOG-based MSM32R Series uses the same SOG base-array architecture as the MSM30R Series, but offers two metal layers instead of three. The semiconductor process is adapted from Oki's production-proven 16-Mbit DRAM manufacturing process. The second-generation 0.5m family retains the high speed and low power of Oki's first-generation 0.5m MSM13R/12R/98R family. The second-generation 0.5m family also shares the same die sizes for arrays with corresponding I/O counts, but the second-generation arrays can contain up to 60% more gates than their first-generation counterparts. The second-generation family is optimized for 3-V core operation, with optimized 3-V I/O buffers and 3-V I/O buffers that are 5-V tolerant, whereas the firstgeneration family offers separate I/O buffers for mixed 3-V and 5-V operation. Oki's first-generation and second-generation 0.5m families together offer an unusually flexible mixed-voltage ASIC capability. The 3-layer-metal MSM30R SOG Series contains 8 array bases, offering up to 448 I/O pads and over 600K raw gates. The 2-layer metal MSM32R SOG Series contains five array bases, offering up to 320 I/O pads and over 300K raw gates. These SOG array sizes are designed to fit the most popular Quad Flat Pack (QFP) and Plastic Ball Grid Array (PBGA) packages. The MSM30R and MSM32R Series' SOG architecture allows rapid prototyping turnaround times, additionally offering the most cost-effective solution for pad-limited circuits (particularly the 2-layer metal MSM32R Series). The 3-layer-metal MSM92R CSA Series contains 36 array bases, offering a wider span of gate and I/O counts than SOG Series. Oki uses the EPOCH memory compiler from Cascade Design Automation to generate optimized single- and dual-port RAM macrocells for CSA designs. As such, the MSM92R Series is suited to memory-intensive ASICs and high-volume designs where fine tuning of package size produces significant cost or real-estate savings.
FEATURES
* * * * * 0.5m drawn two and three-layer metal CMOS Optimized 3.3-V core Optimized 3-V I/O and 3-V I/O that is 5-V tolerant SOG and CSA architecture availability 120-ps typical gate propagation delay (for a 2-input 4x-drive NAND gate with a fan-out of 2 and 0mm of wire, operating at 3.3 V) * Up to 1.2M raw gates and 624 pads * User-configurable I/O with VSS, VDD, TTL, 3-state, and 1 mA ~ 24 mA options * Slew-rate-controlled outputs for low-radiated noise * Clock tree cells with 0.5-ns clock skew, worst-case (fan-out 9000 at 75 MHz) * User-configurable single and dual-port memories * Specialized macrocells, including phase-locked loop, GTL, PECL, and PCI cells * Floorplanning for front-end simulation, back-end layout controls, and link to synthesis * JTAG boundary scan and scan-path ATPG * Support for popular CAE systems, including Cadence, IKOS, Mentor Graphics, Synopsys, Viewlogic, and Zycad
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MSM30R/32R/92R FAMILY LISTING
CSA Part# MSM92RB01 MSM92RB02 MSM92RB03 MSM92RB04 MSM92RB05 -- MSM92RB06 MSM92RB07 MSM92RB08 MSM92RB09 -- MSM92RB10 MSM92RB11 MSM92RB12 -- MSM92RB13 MSM92RB14 MSM92RB15 -- MSM92RB16 MSM92RB17 MSM92RB18 MSM92RB19 -- MSM92RB20 MSM92RB21 MSM92RB22 MSM92RB23 MSM92RB24 MSM92RB25 MSM92RB26 MSM92RB27 MSM92RB28 MSM92RB29 MSM92RB30 MSM92RB31 MSM92RB32 MSM92RB33 MSM92RB34 MSM92RB35 MSM92RB36 CSA Master# B92R020X020 B92R024X024 B92R026X026 B92R030X030 B92R032X032 -- B92R036X036 B92R038X038 B92R040X040 B92R042X042 -- B92R044X044 B92R048X048 B92R050X050 -- B92R052X052 B92R056X056 B92R060X060 -- B92R064X064 B92R068X068 B92R072X072 B92R076X076 -- B92R080X080 B92R084X084 B92R088X088 B92R092X092 B92R096X096 B92R100X100 B92R104X104 B92R108X108 B92R112X112 B92R118X118 B92R122X122 B92R126X126 B92R132X132 B92R138X138 B92R144X144 B92R150X150 B92R156X156 SOG Part# I/O Pads 80 96 104 120 128 144 144 152 160 168 176 176 192 200 208 208 224 240 256 256 272 288 304 320 320 336 352 368 384 400 416 432 448 472 488 504 528 552 576 600 624 Raw Gates 14,688 22,784 27,440 37,720 43,296 56,000 56,000 63,176 70,336 78,352 86,304 86,304 103,904 114,400 123,968 123,968 144,900 167,464 191,660 191,660 217,488 244,948 274,040 306,072 306,072 338,496 372,552 408,240 445,560 484,512 525,096 569,096 613,012 682,644 730,664 780,316 857,072 941,360 1,025,488 1,115,000 1,206,400 Rows 72 89 98 115 123 140 140 149 157 166 174 174 191 200 208 208 225 242 259 259 276 293 310 327 327 344 361 378 395 412 429 446 463 489 506 523 548 574 599 625 650
[1]
Columns 204 256 280 328 352 400 400 424 448 472 496 496 544 572 596 596 644 692 740 740 788 836 884 936 936 984 1032 1080 1128 1176 1224 1276 1324 1396 1444 1492 1564 1640 1712 1784 1856
Usable Gates 11,750 18,227 21,952 30,176 34,637 26,880 42,000 47,382 52,752 58,764 38,837 60,413 72,733 80,080 49,587 86,778 101,430 117,225 72,831 126,496 143,542 161,666 180,866 110,186 195,886 216,637 238,433 261,274 276,247 300,397 325,560 352,840 367,807 409,586 438,398 468,190 514,243 564,816 615,293 669,000 723,840
[2]
--
-- MSM30R0020 -- -- MSM32R0050 MSM30R0050 -- -- -- MSM32R0080 MSM30R0080 -- -- MSM32R0120 MSM30R0120 -- -- MSM32R0190 MSM30R0190 -- -- -- MSM32R0300 MSM30R0300 -- -- -- MSM30R0440 -- -- -- -- -- -- -- -- -- -- -- --
1. Row and column numbers are used to evaluate the number and size of mega macrocells that may be included into each array. 2. Usable gate count is design dependent and varies based upon the number of fan-outs per net, internal busses, floor plan, RAM/ROM blocks, etc.
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ARRAY ARCHITECTURE
The primary components of a 0.5m MSM30R/32R/92R circuit include: * * * * * * * I/O base cells Configurable I/O pads for VDD, VSS, or I/O (optimized 3-V I/O and 3-V I/O that is 5-V tolerant) VDD and VSS pads dedicated to wafer probing Separate power bus for output buffers Separate power bus for internal core logic and input buffers Core base cells containing N-channel and P-channel pairs, arranged in column of gates Isolated gate structure for reduced input capacitance and increased routing flexibility
Each array has 24 dedicated corner pads for power and ground use during wafer probing, with four pads per corner. The arrays also have separate power rings for the internal core functions (VDDC and VSSC) and output drive transistors (VDDO and VSSO).
I/O base cells Configurable I/O pads for VDD, VSS, or I/O
Separate power bus (VDDC, VSSC) for internal core logic (2nd metal/3rd metal
1,2, or 3 layer metal interconnection in core area
Core base cell with 4 transistors
VDD, VSS pads (4) in each corner for wafer probing only
Separate power bus (VDDO, VSSO) over I/O cell for output buffers(2nd metal/3rd metal)
Figure 7. MSM30R0000 Array Architecture MSM92R000 CSA Layout Methodology The procedure to design, place, and route a CSA follows. 1. Select suitable base array frame from the available predefined sizes. To select an array size: - Identify the macrocell functions required and the minimum array size to hold the macrocell functions.
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- Add together all the area occupied by the required random logic and macrocells and select the optimum array. 2. Make a floor plan for the design's megacells. - Oki Design Center engineers verify the master slice and review simulation. - Oki Design Center or customer engineers floorplan the array using Oki's proprietary floorplanner or HLD DP3 and customer performance specifications. - Using Oki CAD software, Design Center engineers remove the SOG transistors and replace them with diffused memory macrocells to the customer's specifications. Figure 8 shows an array base after placement of the optimized memory macrocells.
Early mask high-density ROM
Mega macrocell High-density RAM
Multi-port RAM
Figure 8. Optimized Memory Macrocell Floor Plan 3. Place and route logic into the array transistors. - Oki Design Center engineers use layout software and customer performance specifications to connect the random logic and optimized memory macrocells. Figure 9 marks the area in which placement and routing is performed with cross hatching.
Figure 9. Random Logic Place and Route
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (VSS = 0 V, Tj = 25 C) [1]
Parameter Power supply voltage Input voltage (Normal Buffer) (5V Tolerant Buffer) (Normal Buffer) (5V Tolerant Buffer) (Normal Buffer) (5V Tolerant Buffer) 1mA buffer 2mA buffer 4mA buffer 6mA buffer 8mA buffer 12mA buffer 24mA buffer Symbol VDD VI VO Conditions VDD = +0.3 ~ 3.6V VDD < 3.0V VDD = +0.3 ~ 3.6V VDD < 3.0V Rated Value -0.3 ~ +4.6 -0.3 ~ VDD+0.3 -0.3 ~ 6.0 -0.3 ~ VDD+0.3 -0.3 ~ VDD+0.3 -0.3 ~ 6.0 -0.3 ~ VDD+0.3 -10 ~ + 10 -6 ~ + 6 -6 ~ + 6 -6 ~ +6 -8 ~ +8 -12 ~ + 12 -16 ~ + 16 -24 ~ + 24 -48 ~ + 48 -65 ~ +150 Unit V
Output voltage
Input current Output current
II IO
mA
Storage temperature
Tj
C
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions in the other specifications of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions (VSS = 0 V)
Parameter Symbol Min Power supply voltage Junction temperature Input rise time/fall time Core VDD Tj tr, tf +3.0 -40 Rated Value Typ. +3.3 2 Max +3.6 +85 20 V C ns Unit
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DC Characteristics (VDD = 3.0 V ~ 3.6 V, VSS = 0 V, Tj = -40 C ~ +85 C)
Parameter Symbol Conditions Min High-level input voltage VIH TTL normal input TTL 5V tolerant input TTL normal input TTL 5V tolerant input TTL normal input Vt+ - VtTTL 5V tolerant input Vt+ - VtIOH=-100 A IOH=-1,-2,-4,-6,-8, -12,-24 mA IOH=-100 A IOH=-1,-2,-4,-6,-8, -12 mA IOL=100 A VOL Low-level output voltage (5V tolerant buffer) IOL=1,2,4,6,8,12,24 mA IOL=100 A IOL=1,2,4,6,8,12 mA 2.0 2.0 -0.3 -0.3 0.7 0.4 0.7 0.4 VDD-0.2 2.4 VDD-0.2 2.4 Rated Value Typ [1] Max VDD+0.3 5.5 0.8 0.8 2.0 2.0 0.2 0.4 0.2 0.4 V Unit
Low-level input voltage TTL-level Schmitt Trigger threshold voltage (Normal buffer) TTL-level Schmitt Trigger threshold voltage (5V tolerant buffer) High-level output voltage (Normal buffer)
VIL Vt+ VtVt Vt+ VtVt
High-level output voltage (5V tolerant buffer)
VOH
Low-level output voltage (Normal buffer)
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DC Characteristics (VDD = 3.0 V ~ 3.6 V, VSS = 0 V, Tj = -40 C ~ +85 C) (Continued)
Parameter Symbol Conditions Min High-level input current (Normal buffer) VIH=VDDIO VIH=VDDIO (50k pull down) VIH=VDDIO IIH VIH=VDDIO (50k pull down) VIH=5.5V VIH=5.5V (3k/50k pull up) VIH=5.5V (50k pull down) Low-level_input current (Normal buffer) VIL=VSS VIL=VSS (50k pull up) VIL=VSS (3k pull up) VIL=VSS VIL=VSS (50k pull up) VIL=VSS (3k pull up) 3-state output_ leakage current (Normal buffer) VOH=VDDIO IOZH VOH=VDDIO (50k pull down) VOL=VSS IOZL VOL=VSS (50k pull up) VOL=VSS (3k pull up) 15 15 -1 -170 -3.3 -1 -170 -3.3 15 -1 -170 -3.3 Rated Value Typ [1] 66 66 -66 -1.1 -66 -1.1 66 -66 -1.1 Max 1 170 10 170 10 250 170 -15 -0.3 -15 -0.3 1 170 -15 -0.3 mA A A mA A Unit
High-level input current (5V tolerant buffer)
Low-level_input current (5V tolerant buffer)
IIL
mA
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DC Characteristics (VDD = 3.0 V ~ 3.6 V, VSS = 0 V, Tj = -40 C ~ +85 C) (Continued)
Parameter Symbol Conditions Min 3-state output_ leakage current (5V tolerant buffer) IOZH VOH=VDDIO VOH=VDDIO (50k pull down) VOH=5.5V VOH=5.5V (3k/50k pull up) VOH=5.5V (50k pull down) VOL=VSS IOZL VOL=VSS (50k pull up) VOL=VSS (3k pull up) 15 -1 -170 -3.3 Rated Value Typ [1] 66 -66 -1.1 Max 1 170 10 250 170 -15 -0.3 mA A Unit
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AC Characteristics (VDD = 3.3 V, VSS = 0 V, Tj = 25 C)
Parameter Internal gate propagation delay Driving Type 1X Inverter 2X 4X 1X 2-input NAND 2X 4X 1X Inverter 2X 4X 1X 2-input NAND 2X 4X Toggle frequency Input buffer propagation delay TTL level, normal input buffer F/O= 2, standard wire length F/O= 1, L= 0 mm F/O= 2 , F/O= 2 , L= 0 mm Conditions [1] [2] Rated Value [3] 0.12 0.10 0.08 0.17 0.14 0.12 0.28 0.20 0.13 0.36 0.24 0.17 630 0.41 (typ) MHz ns Unit
TTL level, 5V tolerant input buffer Output buffer propagation delay 4 mA Push-pull, Normal output buffer 3-state, 5V tolerant output buffer Output buffer transition times [4] Push-pull, Normal output buffer 3-state, 5V tolerant output buffer 8 mA 12 mA 4 mA 12 mA
standard wire length CL= 20 pF CL= 50 pF CL= 100 pF CL= 20 pF CL= 75 pF
0.61 (typ) 1.87 (typ) 2.14 (typ) 2.71 (typ) 2.29 (typ) 4.09 (r) (typ) 3.85 (f) (typ) 3.18 (r) (typ) 4.00 (f) (typ) ns
4 mA
CL= 20 pF
1. Input transition time in 0.2ns / 3.3V 2. Typical condition in VDD=3.3V and Tj=25C. 3. Rated value is calculated as an average of the L-H and H-L delay times of each macro type on a typical process. 4. Output rising and falling times are both specified over a 10%-90% range.
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MACRO LIBRARY
Oki Semiconductor supports a wide range of macrocells and macrofunctions, ranging from simple hard macrocells for basic Boolean operations to large, user-parameterizable macrofunctions. The following figure illustrates the main classes of macrocells and macrofunctions available.
Examples Basic Macrocells NANDs NORs EXORs Latches Flip-Flops Combinational Logic
Basic Macrocells with Scan test
Flip-Flops
Clock Tree Driver Macrocells Macrocells 3V, 5V Tolerant Output Macrocells 3-State Outputs Push-Pull Outputs PECL Outputs Counters Shift Registers Open Drain Outputs Slew Rate Control Outputs PCI Outputs
MSI Macrocells
Mega/Special Macrocells [1] Macro Library 3V, 5V Tolerant Input Macrofunctions
UART PLL
82C37 82C54
82C59
PCI Controller Ethernet Controller
Inputs Inputs with Pull-Downs Inputs with Pull-Ups GTL Inputs PECL Inputs
3V, 5V tolerant Bi-Directional Macrofunctions Macrofunctions MSI Macrofunctions
I/O PCI I/O
I/O with Pull-Downs I/O with Pull-Ups
74199 74163
74151
Oscillator Macrofunctions
Gated Oscillators
Memory Macrocells
[1] Under development
SOG RAMs: Single-Port RAMs Dual-Port RAMs
Optimized Diffused RAMs: Single-Port RAMs Dual-Port RAMs
Figure 10. Oki Macrocell and Macrofunction Library
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Macrocells for Driving Clock Trees Oki offers clock-tree drivers that guarantee a skew time of less than 0.5 ns. The advanced layout software uses dynamic driver placement and sub-trunk allocation to optimize the clock-tree implementation for a particular circuit. Features of the clock-tree driver-macrocells include: * * * * * * * * Clock skew 0.5 ns Automatic fan-out balancing Dynamic sub-trunk allocation Single clock tree driver logic symbol Single-level clock drivers Automatic branch length minimization Dynamic driver placement Up to four clock trunks
The clock-skew management scheme is described in detail in Oki's 0.5m Technology Clock Skew Management Application Note.
Clocked Cell Main Trunk Sub Trunk Branch
Clock Drivers
Pad
Input Buffer
Clock Tree Driver Macrocell
Figure 11. Clock Tree Structure
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OKI ADVANCED DESIGN CENTER CAD TOOLS
Oki's advanced design center CAD tools include support for the following: * * * * Floorplanning for front-end simulation and back-end layout control Clock tree structures improve first-time silicon success by eliminating clock skew problems JTAG Boundary scan support Power calculation which predicts circuit power under simulation conditions to accurately model package requirements
Oki Design Kit Availability
Vendor Cadence Syntest Platform Sun(R) [2] Sun(R) [2] Operating System [1] Solaris Solaris Vendor Software/Revision [1] Ambit Buildgates NC-VerilogTM Verilog XL Turbo Fault Design Compiler Ultra + Tetramax/ATPG Primetime DFT Compiler/Test Compiler RTL Analyzer VCS MTI-VHDL MTI-Verilog Floorplanner Conformal Description Design Synthesis Design Simulation Design Simulation Fault Simulation Design synthesis Test Synthesis Static Timing Analysis (STA) Test synthesis RTL check Design Simulation Design Simulation Design Simulation Floor planning Formal Verification
Synopsys
Sun(R) [2]
Solaris
Model Technology Inc. (MTI) Oki Verplex
Sun(R) [2] NT Sun(R) [2] Sun(R) [2]
Solaris WinNT4.0 Solaris Solaris
1. Contact Oki Application Engineering for current software versions. 2. Sun or Sun-compatible.
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Design Process The following figure illustrates the overall IC design process, also indicating the three main interface points between external design houses and Oki ASIC Application Engineering.
Level 1 [4] Synopsys Timing Script (optional) VHDL/HDL Description Synthesis Floorplanning Gate-Level Simulation Functional Test Vectors
CAE Front-End
Level 2 Netlist Conversion (EDIF 200) Scan Insertion (Optional) CDC [1] Floorplanning Formal Verification Pre-Layout Simulation Level 2.5 [4] Layout / Timing Driven Layout (optional) [6] Fault Simulation [5] Automatic Test Pattern Generation Oki Interface Test Vector Conversion (Oki TPL [3]) TDC [2]
Static Timing Analysis
Verification (Design Rule Check/Formal Verification)
Post-Layout Simulation
Level 3 [4] Manufacturing Prototype Test Program Conversion
[1] Oki's Circuit Data Check program (CDC) verifies logic design rules [2] Oki's Test Data Check program (TDC) verifies test vector rules [3] Oki's Test Pattern Language (TPL) [4] Alternate Customer-Oki design interfaces available in addition to standard level 2 [5] Standard design process includes fault simulation [6] Requires Synopsys timing script for Oki timing driven layout
Figure 12. Oki's Design Process
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Automatic Test Pattern Generation Oki's 0.5m ASIC technologies support Automatic Test Pattern Generation (ATPG) using full scan-path design techniques, including the following: * * * * * * * * * Increases fault coverage 95% Uses Synopsys Test Compiler Automatically inserts scan structures Connects scan chains Traces and reports scan chains Checks for rule violations Generates complete fault reports Allows multiple scan chains Supports vector compaction
ATPG methodology is described in detail in Oki's 0.5m Scan Path Application Note.
Combinational Logic A FD1AS D C SD SS Q B FD1AS D C SD SS Q Scan Data Out
Scan Data In
QN
QN
Scan Select
Figure 13. Full Scan Path Configuration Floorplanning Design Flow Oki's floorplanner can be classified as both a front-end floorplanner and a back-end floorplanner. During front-end floorplanning, logic designers use the floorplanner to generate two files: a capacitance file for pre-layout simulation, and a floorplanner interface file for layout. During back-end floorplanning, the layout engineer transfers the floorplanner interface file to Oki's proprietary layout software, code-named Pegasus. The floorplanner interface file contains information about the placement of blocks and groups of blocks. The back-end floorplanner is automated and is transparent to logic designers. Figure 14 shows a diagram of front-end floorplanning. Figure 15 shows a diagram of back-end floorplanning.
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Floorplanner
EDIF EDIF Netlist
Set Design
rcEst Simulation Interface File
Pre-Floor Plan
PLT Pinlist File
Floorplan
FPI Floorplanner Interface File
Figure 14. Front-End Floorplanning
Pegasus
EDIF EDIF Netlist
Pre-Layout
FPI Floorplanner Interface File
GCD
Layout
FIF Layout Interface File
Figure 15. Back-End Floorplanning IEEE JTAG Boundary Scan Support Boundary scan offers efficient board-level and chip-level testing capabilities. Benefits resulting from incorporating boundary-scan logic into a design include: * * * * * * Improved chip-level and board-level testing and failure diagnostic capabilities Support for testing of components with limited probe access Easy-to-maintain testability and system self-test capability with on-board software Capability to fully isolate and test components on the scan path Built-in test logic that can be activated and monitored An optional Boundary Scan Identification (ID) Register
Oki's boundary scan methodology meets the JTAG Boundary Scan standard, IEEE 1149.1-1990. Oki supports boundary scan on both Sea of Gates (SOG) and Customer Structured Array (CSA) ASIC technologies. Either the customer or Oki can perform boundary-scan insertion. More information is available in Oki's JTAG Boundary Scan Application Note. Contact the Oki Application Engineering Department for interface options.
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PACKAGE OPTIONS
MSM30R/32R/92R Package Menu
Product SOG QFP TQFP LQFP PBGA FBGA Name I/O MSM92. MSM MSM Pad . 32R 30R s [1] 44 64 80 100 128 160 208 240 304 44 64 80 100 128 144 176 208 256 352 420 560 144 224 RB01 RB02 RB03 RB04 RB05 80 96 0020 104 120 128
G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G
RB06 0050 0050 144 RB07 RB08 RB09 152 160 168
RB10 0080 0080 176 RB11 RB12 192 200
RB13 0120 0120 208 RB14 RB15 224 240
RB16 0190 0190 256 RB17 RB18 RB19 272 288 304
RB20 0300 0300 320 RB21 RB22 RB23 RB24 RB25 RB26 RB27 RB28 RB29 RB30 RB31 RB32 RB33 RB34 RB35 RB36 336 352 368 0440 384 400 416 432 448 472 488 504 528 552 576 600 624
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MSM30R/32R/92R Package Menu (Continued)
Product SOG QFP TQFP LQFP PBGA FBGA Name I/O MSM92. MSM MSM Pad . 32R 30R s [1] 44 64 80 100 128 160 208 240 304 44 64 80 100 128 144 176 208 256 352 420 560 144 224 Body Size (mm) Lead Pitch (mm) Ball Count Signal I/O Power Balls Ground Balls 1. I/O Pads can be used for input, output, bi-directional, power, or ground. G = Available now; = In development
9x10 14x1414x2014x2028x2828x2828x2832x3240x4010x1010x1012x1214x1414x1420x2024x2428x2827x2735x3535x3535x3513x1315x15
0.8
0.8
0.8 0.65 0.8 0.65 0.5
0.5
0.5
0.8
0.5
0.5
0.5
0.4
0.5
0.5
0.5 1.27 1.27 1.27 1.00 0.8
0.8
256 352 420 560 144 224 231 304 352 400 144 224 12 13 16 32 32 36 80 80 -
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NOTES
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The information contained herein can change without notice owing to product and/or technical improvements. Please make sure before using the product that the information you are referring to is up-to-date. The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges, including but not limited to operating voltage, power dissipation, and operating temperature. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,office automation, communication equipment, measurement equipment, consumer electronics, etc.).These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans. Such applications include, but are not limited to: traffic control, automotive, safety, aerospace, nuclear power control, and medical, including life support and maintenance. Certain parts in this document may need governmental approval before they can be exported to certain countries. The purchaser assumes the responsibility of determining the legality of export of these parts and will take appropriate and necessary steps, at their own expense, for export to another country. Copyright 2002 Oki Semiconductor Oki Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by Oki Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Oki Semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Oki.
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